1. Technical Field
The present invention relates to semiconductor memory apparatus, and in particular, to an apparatus and method of generating an output enable signal for a semiconductor memory apparatus.
2. Related Art
As shown in FIG. 1, an apparatus for generating an output enable signal for a semiconductor memory apparatus according to the related art includes a plurality of output enable signal generators OE GEN CL03 to OE GEN CL10 that commonly receive an external read command RD_CMD and a DLL clock DLL_CLK, each delay the DLL clock DLL_CLK by a predetermined delay time, and each output an output enable signal in accordance with a CAS (Column Address Strobe) latency (Hereinafter, refer to as CL), and a multiplexer OE MUX that selects and outputs one output among the plurality of outputs of the output enable signal generators OE GEN CL03 to OE GEN CL10 in accordance with the CL.
The DLL clock is used to obtain a clock margin for outputting a data output enable signal in accordance with the external read command. Further, the DLL clock has a negative-delay component, that is, the DLL clock is counted before an external clock is counted.
As shown in FIG. 2, the output enable signal generator OE GEN CL10 among the plurality of output enable signal generators consists of a plurality of D flip-flops DFF and a delay chain having a plurality of delay elements DLY. Here, the output enable signal generator OE GEN CL9 has the same structure as the output enable signal generator OE GEN CL10 except that the number of D flip-flops and the number of delay elements are reduced by one, respectively. Similarly, the output enable signal generators OE GEN CL 8 to OE GEN CL 3 can be configured by removing the D flip-flops and the delay elements one-by-one from the same structure as the output enable signal generator OE GEN CL10.
As described above, in the technology according to the related art, the CL is adjusted by counting negative-delay components of an external clock and an internal DLL clock and continuously compensating the count value. A point in time when data is output, that is, a point in time when an output enable signal is generated, is controlled by recompensating the negative delay components of the DLL clock through the delay chain having a time difference on the basis of a current clock.
However, the apparatus for generating an output enable signal for a semiconductor memory apparatus according to the related art has a problem in that a high speed semiconductor memory apparatus is operated at a high frequency and this causes the CL to be increased. If the CL increases, the number of counts increases and the negative delay component increases. Accordingly, a time period for counting a point in time when outputting data decreases, causing the operational frequency to reach the limit.